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| INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: * The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications * The IC06 74HC/HCT/HCU/HCMOS Logic Package Information * The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT137 3-to-8 line decoder/demultiplexer with address latches; inverting Product specification File under Integrated Circuits, IC06 December 1990 Philips Semiconductors Product specification 3-to-8 line decoder/demultiplexer with address latches; inverting FEATURES * Combines 3-to-8 decoder with 3-bit latch * Multiple input enable for easy expansion or independent controls * Active LOW mutually exclusive outputs * Output capability: standard * ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT137 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. 74HC/HCT137 The 74HC/HCT137 are 3-to-8 line decoder/demultiplexers with latches at the three address inputs (An). The "137" essentially combines the 3-to-8 decoder function with a 3-bit storage latch. When the latch is enabled (LE = LOW), the "137" acts as a 3-to-8 active LOW decoder. When the latch enable (LE) goes from LOW-to-HIGH, the last data present at the inputs before this transition, is stored in the latches. Further address changes are ignored as long as LE remains HIGH. The output enable input (E1 and E2) controls the state of the outputs independent of the address inputs or latch operation. All outputs are HIGH unless E1 is LOW and E2 is HIGH. The "137" is ideally suited for implementing non-overlapping decoders in 3-state systems and strobed (stored address) applications in bus oriented systems. QUICK REFERENCE DATA GND = 0 V; Tamb= 25 C; tr = tf = 6 ns TYPICAL SYMBOL tPHL/ tPLH PARAMETER propagation delay An to Yn LE to Yn E1 to Yn E2 to Yn CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD x VCC2 x fi + (CL x VCC2 x fo) where: fi = input frequency in MHz fo = output frequency in MHz (CL x VCC2 x fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC - 1.5 V ORDERING INFORMATION See "74HC/HCT/HCU/HCMOS Logic Package Information". input capacitance power dissipation capacitance per package notes 1 and 2 CONDITIONS HC CL = 15 pF; VCC = 5 V 18 17 15 15 3.5 57 19 21 17 15 3.5 59 ns ns ns ns pF pF HCT UNIT December 1990 2 Philips Semiconductors Product specification 3-to-8 line decoder/demultiplexer with address latches; inverting PIN DESCRIPTION PIN NO. 1, 2, 3 4 5 6 8 15, 14, 13, 12, 11, 10, 9, 7 16 SYMBOL A0 to A2 LE E1 E2 GND Y0 to Y7 VCC NAME AND FUNCTION data inputs latch enable input (active LOW) data enable input (active LOW) data enable input (active HIGH) ground (0 V) multiplexer outputs positive supply voltage 74HC/HCT137 Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol. Fig.4 Functional diagram. December 1990 3 Philips Semiconductors Product specification 3-to-8 line decoder/demultiplexer with address latches; inverting FUNCTION TABLE INPUTS LE H X X L L L L L L L L Notes 1. H = HIGH voltage level L = LOW voltage level X = don't care L H X L L L L L L L L E1 H X L H H H H H H H H E2 X X X L H L H L H L H A0 X X X L L H H L L H H A1 X X X L L L L H H H H H H L H H H H H H H H H H L H H H H H H H H H H L H H H H H H H H H H L H H H H A2 Y0 Y1 Y2 OUTPUTS Y3 stable H H H H H H L H H H Y4 74HC/HCT137 Y5 H H H H H H H L H H H H H H H H H H L H Y6 H H H H H H H H H L Y7 Fig.5 Logic diagram. December 1990 4 Philips Semiconductors Product specification 3-to-8 line decoder/demultiplexer with address latches; inverting DC CHARACTERISTICS FOR 74HC For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: standard ICC category: MSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) 74HC SYMBOL PARAMETER +25 min. typ. tPHL/ tPLH propagation delay An to Yn propagation delay LE to Yn propagation delay E1 to Yn propagation delay E2 to Yn output transition time 50 10 9 50 10 9 30 6 5 58 21 17 55 20 16 50 18 14 50 18 14 19 7 6 11 4 3 3 1 1 3 1 1 max. 180 36 31 190 38 32 145 29 25 145 29 25 75 15 13 65 13 11 65 13 11 40 8 7 -40 to +85 min. max. 225 45 38 240 48 41 180 36 31 180 36 31 95 19 16 75 15 13 75 15 13 45 9 8 -40 to +125 min. max. 270 54 46 285 57 48 220 44 38 220 44 38 110 22 19 ns 74HC/HCT137 TEST CONDITIONS UNIT VCC WAVEFORMS (V) 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Fig.6 tPHL/ tPLH ns Fig.7 tPHL/ tPLH ns Fig.7 tPHL/ tPLH ns Fig.6 tTHL/ tTLH ns Fig.6 tW LE pulse width HIGH set-up time An to LE hold time An to LE ns Fig.8 tsu ns Fig.8 th ns Fig.8 December 1990 5 Philips Semiconductors Product specification 3-to-8 line decoder/demultiplexer with address latches; inverting DC CHARACTERISTICS FOR 74HCT For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: standard ICC category: MSI Note to HCT types 74HC/HCT137 The value of additional quiescent supply current (ICC) for a unit load of 1 is given in the family specifications. To determine ICC per input, multiply this value by the unit load coefficient shown in the table below. INPUT An E1 E2 LE UNIT LOAD COEFFICIENT 1.50 1.50 1.50 1.50 AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) 74HCT SYMBO L PARAMETER min. tPHL/ tPLH tPHL/ tPLH tPHL/ tPLH tPHL/ tPLH tTHL/ tTLH tW tsu th propagation delay An to Yn propagation delay LE to Yn propagation delay E1 to Yn propagation delay E2 to Yn output transition time LE pulse width HIGH set-up time An to LE hold time An to LE +25 typ. 22 25 20 18 7 10 10 7 5 2 2 max. 38 44 37 35 15 13 13 9 -40 to +85 min. max. 48 55 46 44 19 15 15 11 -40 to +125 min. max. 57 66 56 53 22 ns ns ns ns ns ns ns ns 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 Fig.6 Fig.7 Fig.7 Fig.6 Fig.6 Fig.8 Fig.8 Fig.8 UNIT VCC WAVEFORMS (V) TEST CONDITIONS December 1990 6 Philips Semiconductors Product specification 3-to-8 line decoder/demultiplexer with address latches; inverting AC WAVEFORMS 74HC/HCT137 (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.6 Waveforms showing the address input (An) and enable inputs (E2) to output (Yn) propagation delays and the output transition times. Fig.7 Waveforms showing the enable input (E1, LE) to output (Yn) propagation delays and the output transition times. The shaded areas indicate when the input is permitted to change for predictable output performance. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.8 Waveforms showing the data set-up, hold times for An input to LE input and the latch enable pulse width. APPLICATION INFORMATION Fig.9 6-to-64 line decoder with input address storage. December 1990 7 Philips Semiconductors Product specification 3-to-8 line decoder/demultiplexer with address latches; inverting PACKAGE OUTLINES See "74HC/HCT/HCU/HCMOS Logic Package Outlines". 74HC/HCT137 December 1990 8 |
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